Logic-Level Optimization of a Reversible Binary Adder Circuit for Low-Energy Computation

Abstract

Reversible logic enables low-energy computation by eliminating information loss, which is a fundamental source of energy dissipation in conventional digital circuits. Binary adders are essential components of arithmetic units and significantly impact overall computational efficiency. Existing reversible binary adder designs often exhibit high quantum cost, excessive garbage outputs, and increased circuit complexity, limiting their suitability for practical low-energy computing systems. This work proposes a logic-level optimized reversible binary adder circuit. Boolean expressions are reformulated at the logic level before reversible gate mapping to minimize quantum cost, garbage outputs, constant inputs, and gate count. The design is analytically modeled and verified through exhaustive simulation. Comparative performance analysis demonstrates a reduction in quantum cost, garbage outputs, and gate count compared with representative reversible adder designs reported in the literature. The proposed logic-level optimized reversible binary adder provides improved energy efficiency and structural simplicity, making it a promising building block for low-energy and quantum-inspired computing systems.